The KSZMNX offers the industry-standard GMII/MII Media Independent Interface (GMII) is compliant to the IEEE Specification. Dave Fifield [email protected] GMII Electrical Specification IEEE Interim Meeting, San Diego, January N. Interface) for connection to GMII/MII MACs in Gigabit . Clarified power cycling specification to have all supply voltages to the KSZMNX.

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By using this site, you agree to the Terms of Use and Privacy Policy. The MAC may omit the signal if it has no use for this functionality, in which case the signal should be tied low for the PHY.

Media-independent interface – Wikipedia

However, at 1 ns edge rates a trace longer than about 2. The standard MII features a small set of registers: Current revisions of IEEE On the other hand, newer devices may support 2. This interface requires 9 signals, versus MII’s When no clock can be recovered i.

Transmit error may be raised for one or more clock periods during frame transmission to request the PHY to deliberately corrupt the frame in specificatiom visible way that precludes it from being received as valid. As such it consists of a preamble, start frame delimiter, Ethernet headers, protocol specific data and a cyclic redundancy check CRC.


These registers can be used to configure the device say “only gigabit, full duplex”, or “only full duplex” or can be used to determine the current operating mode. Given trends in the semiconductor industry and the fact that both ICs are usually on the same board, lack of 5 V tolerance is probably very common, and chips that actually drive 5 V are probably even rarer.

The original MII design has been extended to support reduced signals and increased speeds. More recently, raising transmit error outside frame transmission is used to indicate the transmit data specificattion are being used for special-purpose signalling. At least the standard says the signals need not be treated as transmission lines. It is not to be confused with RM2.

Media-independent interface

This page was last edited on 19 Novemberat The transmit enable signal is held high during frame transmission and low when the transmitter is idle. Source-synchronous clocking is used: There are 32 addresses, each containing 16 bits. From Wikipedia, the free encyclopedia.

For receive, two data values are defined: Ethernet family of local area network technologies. The specification states that inputs should be 5 V tolerant, however, some popular chips with RMII interfaces are not 5 V tolerant. Retrieved 20 April The slecification clock is much simpler, with only one clock, which is recovered from the incoming data.


Transmit and receive path each use one differential pair for data and another differential pair for clock. This means a slight modification of the definition of CRS: Typically used for on-chip connections; in chip-to-chip usage mostly replaced by XAUI.

Four things were changed compared to the MII standard to achieve this:. Reference clock may be an input on both devices from an external clock source, or may be driven from the MAC to the PHY.

Views Read Edit View history. The RMII signals are treated as lumped signals rather than transmission lines; no termination or controlled impedance is necessary; output drive and thus slew rates need to be specufication slow as possible rise times from 1—5 ns to permit this.

Ethernet Computer buses Serial buses. Received clock signal recovered from incoming received data.